1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device including a pattern layer having different minimum feature sizes formed by using an image forming beam such as an optical beam and an electron beam.
2. Description of the Related Art
In a method for manufacturing a semiconductor device, photolithography technology or electron beam exposure technology has been used to form a fine pattern layer. For example, in the photolithography technology, if .lambda. is the wavelength of an optical source and NA is the numerical aperture of a lens of a projector, then a resolving power R is represented by EQU R=k.sub.1 .lambda./NA
where k.sub.1 is constant dependent upon a photoresist process. Therefore, in manufacturing an ultra-large scale integrated (ULSI) circuit using a half-micron design rule, or the like, the wavelength of the optical sources has been changed from .lambda.=436 nm (g-line) to .lambda.=365 nm (i-line) to thereby enhance the resolution power R. PA1 where k.sub.2 is also a constant dependent upon the photoresist process, the depth of focus has been reduced as the resolution power R has been increased.
However, since depth of focus (DOF) is represented by EQU DOF=k.sub.2 .lambda./(NA).sup.2
At the same time, in order to obtain a fine-structured, multi-functional and highly-functional ULSI circuit, the surface of a layer has been made very rough, i.e., a largely-stepwise layer has been formed. As a result, a substantial resolution power has been reduced as compared with the original resolution power. Therefore, only a less fine-structured pattern can be resolved. For example, in a stacked-capacitor-type dynamic random access memory (DRAM), a capacitor electrode made of polycrystalline silicon is made thick enough to compensate for a reduction of its capacitance due to its fine structure. As a result, a step larger than 1 .mu.m is generated in insulating layer between a memory cell portion and a peripheral portion thereof. This reduces the resolution power.
Thus, in a semiconductor device including a largely stepwise layer, the minimum feature size is larger than originally determined by the resolution power of the optical source or electron beam, and therefore, the minimum feature size cannot be reduced.
In order to substantially reduce the minimum feature size for a largely-stepwise layer, a first prior art method uses a photomask (or reticle) that has two different level optical shields (see JP-A-SHO60-7431). This will be explained later in detail. In the first prior art method, however, it is difficult to manufacture such a photomask (or reticle) for a continuous stepwise surface portion of the stepwise layer. This reduces the manufacturing yield and increases the manufacturing cost.
A second prior art method uses a photomask (or reticle) formed by a glass substrate, a phase shift layer formed on the glass substrate, and an optical shield layer formed on the phase shift layer (see JP-A-HEI1-147458). This will be also explained later in detail. In the second prior art method, however, the thickness or refractive index of the phase shift layer has to be changed in accordance with the level of the stepwise layer, which reduces time manufacturing yield and increases the manufacturing cost. Also, the selection of material for the phase shift layer is difficult.